Square wave regenerator



Oct. 28, 1958 P. E. LE F EVRE SQUARE WAVE REGENERATOR Filed July 14, 1955 Voltage 2 Sheets-Sheet 1 e To Received Square wove Signals ya Cl pping P. E. LE F EVRE SQUARE WAVE REGENERATOR Oct. 28, 1958 Filed July 14, 1955 2 Sheets-Sheet 2 B 54 gas P Input H" WI L a, Differ Lntioto r Flip-Flop Inhibit Gate [Limiter ENVENTOR PererELeFevre.

ATTORN EY States Unite sonann WAVE REGENERATOR .etpplication'duly 14, 1955, Serial No. 522,124 8 Ciaims. (Cl. 250-27) This invention relates to devices for reshaping a distorted wave form and, more particularly, to devices for reshaping distorted square wave signals.

When on-ofi information at telegraph or higher speeds is transmitted, the square Wave output of the transmitter suffers distortion in the transmission process during passage through lines and frequency multiplexing filters. This condition presents the problem of reshaping the original signal so that it will be in its original form after passage through a receiver. Reshaping has been accomplished heretofore by the use of relays; however, this method is practicable at low speeds only. Another method which has been used involves saturation of the distorted signal and amplitude clipping. Saturation and clipping can be used at high speeds, but this method is practicable only if inaccuracies up to 1.0% in the resulting wave form can be tolerated.

it is an object of my invention to provide means in an otf-on transmitting system for reshaping a square wave signal so that it assumes the same true square wave form which it had before transmission.

Another object of my invention lies in the provision of means for reshaping a series of square wave signals having different phase widths or time durations.

A still further object of my invention lies in the provision of novel means for controlling operation of a ,bistable flip-flop circuit.

The above and other objects and features of my invention will become apparent from the following detailed description taken in connection with the accompanying drawings which form a part of this specification, and in which:

Figure l is a graphical illustration showing samples of distorted square wave signals together with the effect of attempting to regenerate the original signal by saturation' and clipping methods;

Fig. 2 is a schematic diagram ,of my new and improved regenerator; and

Fig. 3 is a graphical illustration of the operation of the regenerator shown in Fig. 2.

Referring to Fig. 1, two square vWave signals A and B having different amplitudes are shown in their distorted form after passage through line and filter net- ,works. The original time duration or phase width of the transmitted signals was T It can be seen that due to the effect of the line and filter networks, the time duration of the constant voltage portion of the received signals is greatly reduced. :One possible method of ;increasing the time durations T and T of the constant voltage portions of the received signals is by clipping at a Voltage level E. This method, however, still leaves the received signal greatly distorted. Another method of increasing the time duration of the constant voltage portionof the square Wave signal is by saturation followed by clipping. By saturating the signal before it is clipped, the width of the pulses is increased somewhat at the voltage level E. Although the latter method presents a substantial improvement over the former, the resulting waveform is still greatly distorted. The ideal output wave form C is shown in dotted outline.

My new and improved regenerator for producing an output wave form similar to wave form C shown in Fig. 1 is illustrated schematically in Fig. 2. Distorted input square wave signals are applied through a limiter and differentiator to a flip-flop circuit. The limiter comprises a pentode 10 having control, screen, and suppressor grids included therein. As illustrated, the cathode of pentode 10 is connected to ground through a resistor 12 and bypass condenser 14, and its anode is connected to the positive terminal of an anode voltage source, not shown, through resistor 16. Resistors 18 and 1236 provide the necessary bias for the screen grid of the pentode, and the suppressor grid is connected to the cathode as shown. The output of pentode It is applied to the control grid of a triode 22 through the RC differentiator which comprises capacitor 24 and resistor 26 in series. As is well known to those skilled in the art, a difierentiator is a circuit in which the voltage amplitude at the output is proportional at any instant to the rate of change of voltage amplitude at the input. The voltage wave form applied to the grid of triode 22 will, therefore, be a series of sharp voltage pulses which occur in time at the points Where the input square wave signal changes from one voltage level to the other.

Triode 22 and a second triode 28 are contained within the same envelope, and these two tubes are included in the flip-flop circuit referred .to above. The fiip-fiop circuit is a form of multivibrator which employs direct coupling between the plates and grids of two electron discharge tubes. That is, the plate of triode 22 is connected through resistor 30 to the grid of triode 28, and the plate of triode 28 is connected to the grid of triode 22 through resistor 32. The cathodes of triodes 22 and 28 are connected through a common resistor 34 and bypass capacitor 36 to ground, and their anodes are conuected to the positive terminal of the aforesaid anode voltage source through resistors 38 and 40. V

The flip-flop is a circuit possessing two conditions of stable equilibrium. One condition is when triode 22 is conducting and triode 28 is cut oh; the other when triode 28 is conducting and triode 22 is cut 013?. The circuit remains in one or the other of these two conditions until some action occurs which causes the nonconducting tube to conduct. The tubes then reverse their functions and remain in the new condition as long as no plate current flows in the cut 01f tube. The operation of the circuit is based on the fact that when triode 22, for example, is conducting the negative potential on its plate is applied through resistor 30 to the grid of triode 28, thereby preventing conduction through this tube. Conversely, when triode Z8 conducts, the negative potential on its plate will be applied through resistor 32 to the grid of triode 22, thereby cutting it off.

The bias on the control grid of triode 28 is controlled by the output of a counter shown in the right-hand ,portion of Fig. 2. Application of the output of the counter to the grid of the triode 28 is controlled by an inhibit gate which comprises a diode 42 having its cathode connected through resistor 44 to the control grid of pentrode 10. The counter is essentially a frequency divider. That is, it will produce an output pulse for every nth input pulse where n is some predetermined number. In the embodiment shown in Fig. 2, the counter comprises three bistable scale-of-two counters A, B and C connected in cascade. The number of scale-oftwo counters, however, may be varied to suit requirements. Each of the scale-of-two counters will produce an output pulse for every other input pulse applied thereto. The overall scaling or dividing ratio n is the product of the individual counter scaling ratios. In this instance, the counter scaling ratio of each of the counters A, B and C is 2. Therefore, since we have three scale of-two counters connected in cascade in the present embodiment, n=2 2 2=8. Or, in other words, the counter will produce an output pulse for every eight input pulses applied thereto. It should be understood that the particular counter shown and described herein is representative of only one type of counter and that any other suitable counter circuit may be used in its place.

Each of the scale-of-two counters A, B, or C of the present embodiment is a bistable multivibrator similar in construction to the flip-flop circuit already described; The counter A, for example, comprises two triodes 46 and 48 contained within a single envelope. The cathodes of triodes 46 and 48 are both connected to ground through resistor 50 and bypass capacitor 52, and their anodes are connected to a source of anode voltage through resistors 54 and 56, respectively. The plate of triode 48 is connected to the grid of triode 46 through resistor 58; and the plate of triode 46 is connected through resistor 60 to the grid of triode 48. In this manner, only one of the two triodes can conduct at any one time. Input voltage pulses are applied simultaneously to the grids of tubes 46 and 48 through input capacitor 62 and resistor 64, one terminal of resistor 64 being connected to the grids through resistors 66 and 68. It can be shown that before counter B will switch from one stable state to the other, counter A will have to switch from one stable state to the other twice. Further, before counter C will switch from one stable state to the other, counter A will have to switch stable states four times, and counter B will have to switch stable states twice. In this manner, one output voltage pulse is obtained every eight input pulses applied to counter A. The output of the counter is applied through coupling capacitor 70, the diode 42 and resistor 72 to a second RC differentiating circuit comprising capacitor 74 and resistor 76. Therefore, sharp voltage pulses of extremely short time duration (like those from the differentiator of elements 24 and 26) will be applied to the grid of triode 28.

It is important to note that the output of the counter cannot be applied to the grid of triode 28 if diode 42 is biased in the reverse direction by a suflicient amount.

Since the cathode of the diode is connected to the grid of pentode 10, a reverse bias will be applied to the diode preventing signal passage therethrough during the time that a positive input voltage pulse appears on the control grid of pentode 10.

Input voltage pulses for the counter are supplied by an oscillator 78. This oscillator is coupled through capacitor 80 and a second diode 82 to the control grids of the triodes 46 and 48 in the first scale-of-two counter A. The cathode of diode 82 is connected to a source of positive voltage 84 through resistor 86, and the anode of diode 82 is connected through resistor 88 to the anode of triode 22. Under normal conditions, when triode 22- is conducting and its plate potential is lowered, diode 82 will be biased in the reverse direction by the combination of the anode voltage of triode 22 and the voltage from source 84. However, when triode 22 is cut ofi, its plate voltage will rise to a point where the diode 82 will conduct to apply the output of oscillator 78 to the first scale-of-two counter A. The output from the regenerator is taken between the anode of triode 22 and ground.

Operation of the circuit may best be understood by reference to Fig. 3 where the original transmitted square wave signal is illustrated as wave form A. After passage through line and filter networks, the received signal is distorted and appears as wave form B. This is the signal that is applied to the control grid of pentode shown in Fig. 2. After passage through pentode 10, the signal is inverted and limited in amplitude (wave form C). After passing through the difierentiator of elements 24 and 26, the signal appears as wave form D. Note that sharp voltage pulses 110, 112, 114, 116, etc., of extremely short duration are produced by the differentiator when the voltage level of the limited square wave signal suddenly changes from one value to another. The first sharp negative voltage pulse will cut off triode 22 and initiate conduction in triode 28. The resulting rise in plate potential of triode 22 opens diode 82 which, in turn, applies the output of oscillator 78 to the counter. The output of the oscillator as applied to the counter is shown as wave form E in Fig. 3. After a predetermined number of cycles of the oscillator output (in this case, eight), the output of the counter (wave form P) will pass through one cycle. If the output of the counter is applied directly to a differentiator such as the differentiator of elements 74 and 76, a sharp negative voltage pulse will be produced every time the counter output changes from its higher to its lower voltage level. However, due to the action of the inhibit gate, the output of the counter will be cut oil from the ditferentiator whenever a positive input voltage pulse is applied to the control grid of pentode 10. Operation of the inhibit gate is shown by wave form G in Fig. 3. In order to simplify explanation of the process, all of the output voltage pulses of the counter are shown in differentiated form or in wave form G even though some of these output pulses never reach the differentiator. Note that a permanent negative bias is applied to the anode of diode 42 by virtue of its connection to ground through resistor 72. When a positive voltage pulse is applied to the control grid of pentode 10 and the cathode of diode 42, the resulting reverse bias on the diode will inhibit the output of the counter and prevent it from reaching the difierentiator of elements 74 and 76. Therefore, a negative voltage pulse can be applied to the grid of triode 28 only between successive input voltage pulses. In wave form G it can be seen that when the first output voltage pulse 118 from the counter occurs, the diode 42 will be open since at this time the voltage level of the input signal has fallen to its lower value. Therefore, the inhibit gate will pass the difierentiated negative voltage output pulse 118 of the counter to the grid of tube 28, thereby cutting off tube 28 and initiating conduction in tube 22. When tube 22 conducts, it in turn cuts off diode 88 and thus disconnects oscillator 78 from the counter (time T This condition will exist until the next input voltage pulse is applied to pentode 10 (time T When this occurs, triode 22 will again be cut off and oscillator 78 will be connected to the counter via diode 82. At the end of one count (i. e., after eight cycles of the oscillator), the counter will produce an output pulse 120. However, as can be seen from wave form G, the input signal is at its upper voltage level during this time; and, therefore, diode 42 will be cut off and will not pass the signal to the grid of triode 28. The counter will produce another output pulse 122 after another eight cycles of the oscillatory input signal. At this time (t it can be seen that the voltage level of the input signal is at its lower level; therefore, diode 42 is open and will pass a differentiated output'pulse 122 to the grid of triode 28 to cut off the same' and initiate conduction in triode 22. When the third voltage pulse in the input signal is received triode 22 will again be cut off, and oscillator 78 will be connected to the counter through diode 82. In this case, however, the phase width or time duration of the input signal and, consequently, the time during which diode 42 is biased in the reverse direction extends over the time which it takes to produce two output voltage pulses 124 and 126 from the counter. The voltage level of the input signal does not fall to its lower value in this case until just before a third output pulse 128 is produced by the counter, Diode 42, being open at this time, will pass the third differentiated pulse 128 to the grid of tube 28, thereby reversing the flip-flop circuit to its original condition.

It is readily apparent that the voltage existing between the plate and cathode of triode 22, in the above process (wave form H in Fig. 3.). is a. square wave which corresponds to the original transmitted square wave signal. The circuit has an inherent overall delay i in the time between the start of the. transmitted signal (wave form A) and the saturation voltage of the limiter (wave form C). This delay is determined by the characteristics of the filters through which the signal passes and noise considerations. The width of the voltage pulses of the reproduced signal will, of course, be a function of the count of the counter circuit. That is to say, the phase width of each of the output square wave voltage pulses (wave form H) will be an integral multiple of the count of the counter. The first regenerated square wave pulse has a time duration equal to one count; the second pulse has a time duration equal to two counts; the third pulse has a time duration equal to three counts; and so on. It can be seen that if the phase widths of the original transmitted pulses are not equal to an integral multiple of the count of the counter, then the phase width of the regenerated signals will not be identical to that of the original signals. The percentage error in this case can be minimized by decreasing the count.

Although I have described my invention in connection with a specific embodiment, it should be apparent to those skilled in the art that various changes in form and arrangement of parts may be made to suit requirements without departing from the spirit and scope of the invention. In this respect, it should be apparent that semiconductor devices can be substituted for the vacuum tubes used in the embodiment of the invention shown.

I claim as my invention:

1. In combination with a source of voltage pulses, a first electron discharge device having an anode, cathode and control electrode included therein, means for applying said voltage pulses between the control electrode and cathode of said first device, second and third electron discharge devices each having an anode and control electrode included therein, a connection between the anode of said second device and the control electrode of said third device, a connection between the anode of said third device and the control electrode of said second device, means including a capacitor and a resistor in series connecting the anode of said first device to the control electrode of said second device, a counter circuit having input and output terminals, means including a first unidirectional current device coupling one of said output terminals to the control electrode of said third device, a connection between the control electrode of said first device and the cathode of said first unidirectional current device, an oscillator having a pair of output terminals, means including a second unidirectional current device coupling an ouput terminal of said oscillator to an input terminal of said counter circuit, and a connection between the anode of said second discharge device and the anode of said second unidirectional current device.

2. The combination claimed in claim 1 in which the cathode of said first unidirectional current device is coupled to the said one output terminal of said counter circuit, and in which the cathode of said second unidirectional current device is coupled to said input terminal of said counter circuit.

3. In combination with a source of voltage pulses and an oscillator, first, second and third electron valves each having an input terminal and an output terminal, a control element included in each of said valves for varying current flow therethrough in response to variations in a voltage applied between said input terminal and said element, means connecting the input terminals, of said.

secondand third valves, means connecting the control element of said second valve to, the output terminal of said third valve and vice versa, means for coupling the output terminal of said first valve to the control element of said second valve, a device for dividing the frequency of an applied input signal, means including a first unidirectional current device for applying the output of saidfrequency dividing device between the input terminal and control element of said third electron valve, means including a second unidirectional current device for applying the output of said oscillator to said frequency dividing device, each of, said unidirectional current devices having a pair of terminals adapted for connection to a current-carrying path, means connecting the control element of said first valve to one terminal of said first unidirectional current device, and means connecting the output terminal of said second valve to one terminal of said second unidirectional current device.

4. In combination with a source of voltage pulses, means for limiting the amplitude of said voltage pulses, a bistable flip-flop circuit, means for deriving an output voltage from said flip-flop circuit when it assumes one of its two stable states, means for coupling said limiting means to said flip-flop circuit so that a voltage pulse applied to said limiter will cause said flip-flop circuit to assume its said one stable state, a device for dividing the frequency of an oscillatory signal applied thereto, means including a first unidirectional current device for applying an oscillatory input signal to said frequency dividing device, means including a second unidirectional current device for applying the output of said frequency dividing device to said flip-flop circuit so that a negative output voltage pulse from said divider will cause said flip-flop circuit to assume its other stable state, means for applying said voltage pulses between the anode and cathode of said second unidirectional current device, and means for applying the output of said flip-flop circuit between the anode and cathode of said first unidirectional current device.

5. The combination claimed in claim 4 in which the means for coupling the limiting means to the flip-flop circuit comprises a dilferentiating circuit.

6. In combination with a source of voltage pulses, means for limiting the amplitude of said voltage pulses, a bistable flip-flop circuit, means for deriving an output voltage from said flip-flop circuit when it assumes one of its two stable states, means for coupling said limiting means to said flip-flop circuit so that a voltage pulse applied to said limiter will cause said flip-flop circuit to assume its said one stable state, a device for dividing the frequency of an oscillatory signal applied thereto, means for applying an oscillatory input signal to said frequency dividing device, means for applying the output of said frequency dividing device to said flip-flop circuit to thereby cause said flip-flop circuit to assume its other stable state, means responsive to the output voltage from said flip-flop circuit for controlling application of said oscillatory signal to said frequency dividing device, and a device responsive to said voltage pulses for controlling application of the output of said frequency dividing device to said flip-flop circuit.

7. In combination with a source of voltage pulses, a bistable flip-flop circuit, means for deriving an output voltage from said flip-flop circuit when it assumes one of its two stable states, means responsive to said voltage pulses for causing said flip-flop circuit to assume its said one stable state, a device for dividing the frequency of an oscillatory signal applied thereto, means for applying an oscillatory input signal to said frequency dividing device, means for applying the output of said frequency dividing device to said flip-flop circuit to assume its other stable state, means responsive to the output voltage of said flip-flop circuit for controlling application of said oscillatory signal to said frequency dividing device, and a device responsive to said voltage pulses for controlling application of the output of said frequency dividing device to said flip-flop circuit.

8. In combination with a source of voltage pulses, a o bistable flip-flop circuit, means for deriving an output voltage from said flip-flop circuit when it assumes one of its two stable states, means responsive to said voltage pulses for causing said flip-flop circuit to assume its said one stable state, a device for dividing the frequency 10 of an oscillatory input signal applied thereto, means for applying an oscillatory input signal to said frequency dividing device, means for applying the output of said frequency dividing device to said flip-flop circuit'to thereby cause the flip-flop circuit to assume its other stable 5 state, and a device for controlling application of the output of said frequency dividing device to said flip-flop circuit.

References Cited in the file of this patent UNITED STATES PATENTS 

